Abstract:
Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping
admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep
learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of
results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable
alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (GDI) logic is one of the
prompting alternatives to CMOS logic to reduce transistors and low-power design. In this work, a novel energy and area efficient
1-bit GDI-based full swing Energy and Area efficient Full Adder (EAFA) with minimum error distance is proposed. +e proposed
architecture was constructed to mitigate the cascaded effect problem in GDI-based circuits. It is proved by extending the proposed
1-bit GDI-based adder for different 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA) segmented
as accurate and inaccurate adder circuits. +e proposed adder’s design metrics in terms of delay, area, and power dissipation are
verified through simulation using the Cadence tool. +e proposed logic is deployed to accelerate the convolution process in the
Low-Weight Digit Detector neural network for real-time handwritten digit classification application as a case study in the Intel
Cyclone IV Field Programmable Gate Array (FPGA). +e results confirm that our proposed EAHSETA occupies fewer logic
elements and improves operation speed with the speed-up factor of 1.29 than other similar techniques while producing 95% of
classification accuracy
